FPGA数字时钟的verilog代码实现

FPGA数字时钟的verilog代码实现

主体功能代码参考了学长的实验报告，并且把里面屎山代码的部分（变量名和排版）优化了一遍。

主功能模块 top_clock.v

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
module clock(
input CP,CR,EN,stop,setclock,dangwei,adjmode,mode,seta,startalarm,showmode,set,setmode,  //CR清零，EN熄屏，stop停止计时，setclock调整时钟开关，dangwei切换小时/时间调整，adjmode切换加减调整,mode切换显示时间、闹钟,seta调整闹钟开关,startalarm开启关闭闹钟,showmode12、24小时显示切换,set手动调整CP输入,setmode切换手动、自动调整
output [6:0] show,                                           
output [7:0] guan,
output alarmLED,
output alarmsound,
output alarmonLED,
output alarmsoundEN,
output zhengLED
    );//CP时钟，CR置零，EN停止显示，stop时钟停止，show显示的部分，guan显示的数码管
wire [7:0] miao,fen,hour;//存放秒、分、时
wire [7:0] alarmfen,alarmhour;
wire [3:0] number;//存放显示的数字
wire JIN1,JIN2;//JIN1秒进分，JIN2分进时(时钟模式下)
wire CP2,CP1,CP0;//CP1 1hz,CP0 1000hz,CP2 约3hz
wire alarmCP;//闹钟声音与LED控制信号
wire CPCLOCK,CPALARM; //控制时钟、闹钟+-的信号
wire psetclock,pseta;  //防抖动后的信号
assign CPCLOCK=(~psetclock&&setmode)?set:CP1;  //手动调整模式下，CPCLOCK和CPALARM由set开关产生
assign CPALARM=(~pseta&&setmode)?set:CP1;
assign JIN1=(miao[3:0]==4'b1001&&miao[7:4]==4'b0101)||((~setclock)&&mode);         //产生时钟进分信号，当在时钟模式下设置时或到59秒
assign JIN2=(fen[3:0]==4'b1001&&fen[7:4]==4'b0101&&miao[3:0]==4'b1001&&miao[7:4]==4'b0101)||((~setclock)&&mode);//产生时钟进时信号，当在时钟模式下设置时或到59分59秒
assign alarmLED=alarmCP;  //闹钟LED
assign alarmonLED=startalarm;  //显示闹钟是否开启LED
assign alarmsoundEN=startalarm;  //声音输出使能端
hz1000 U0(CP,CP0);   //产生1000hz
pinglv U1(CP0,CR,stop,CP1); //产生1hz
miao U2(CP1,CR,miao[7:4],miao[3:0]); //秒记录
fenzhong U3(CPCLOCK,CR,setclock,dangwei,adjmode,JIN1,fen[7:4],fen[3:0]); //分记录
hour U4(CPCLOCK,CR,setclock,dangwei,adjmode,JIN2,hour[7:4],hour[3:0]); //时记录
xianshi U5(number,show); //显示管控制
showtime U6(CP0,EN,mode,showmode,miao,fen,hour,alarmfen,alarmhour,number,guan);  //显示控制
setalarm U8(CPALARM,CR,seta,dangwei,adjmode,mode,alarmfen[7:4],alarmfen[3:0],alarmhour[7:4],alarmhour[3:0]);//设置闹钟
alarm U9(CP0,CR,startalarm,seta,setclock,fen,hour,alarmfen,alarmhour,alarmCP); //闹钟模块
galarmsound U10(CP,alarmCP,startalarm,alarmsound); //产生闹钟声音
zheng U11(CP2,CR,setclock,showmode,fen,miao,hour,zhengLED); //整点报时模块
zhengCP U12(CP0,CP2); //产生整点报时的CP信号,约3HZ
prevent U13(CP0,0,0,setclock,psetclock);//防抖动
prevent U14(CP0,0,0,seta,pseta); //防抖动
endmodule

endmodule

分频为1khz

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
module hz1000(
input CP,
output reg CLK=0
    );
reg [15:0] state;
always@(posedge CP)
begin
 if(state<49999) state<=state+1'b1;//由1MHZ脉冲产生1KHZ脉冲，每计数50000输出翻转一次
 else 
 begin
 CLK<=~CLK;
 state<=0;
 end
end
endmodule

分频为1hz

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
module pinglv(
input CP,CR,stop,
output reg CLK
    );
reg [8:0] state;
always@(posedge CP,negedge CR)
begin
 if(~CR)
 begin
  CLK<=0;
  state<=0; 
 end
 else if(~stop)                  //stop可以控制使得停止计时（便于调整秒）
 begin
  CLK<=CLK;
  state<=state;
 end
 else if(state<499) state<=state+1'b1; //由1kHZ脉冲产生1HZ脉冲，每计数500输出翻转一次
 else 
 begin
 CLK<=~CLK;
 state<=0;
 end
end
endmodule

秒计数

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
module miao(
input CP,CR,
output reg [3:0] fen1,fen0
    );
always @(posedge CP,negedge CR)   //1Hz脉冲控制，秒分情况+1
begin
if(~CR) 
 begin
 fen1<=0;
 fen0<=0;
 end
else if(fen1<6&&fen0<9) fen0<=fen0+1'b1;
else if(fen1<5&&fen0==9)
 begin
 fen0<=0;
 fen1<=fen1+1'b1;
 end
else
 begin
 fen1<=0;
 fen0<=0;
 end
end
endmodule

分计数

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
module fenzhong(
input CP,CR,setclock,dangwei,adjmode,JIN1,
output reg [3:0] fen1,fen0
    );
always @(posedge CP,negedge CR)
begin
if(~CR)                                       //清零
 begin
 fen1<=0;
 fen0<=0;
 end
 
else if(JIN1==0);                            //无进位信号保持

else if({setclock,dangwei,adjmode}==3'b000)  //在设置分钟模式且调整模式为减时，分钟分情况-1
begin
if(fen0>0) fen0<=fen0-1'b1;
else if(fen1>0&&fen0==0)
 begin
 fen0<=4'b1001;
 fen1<=fen1-1'b1;
 end
else
 begin
 fen1<=4'b0101;
 fen0<=4'b1001;
 end
end

else if(setclock==0&&dangwei==1);               //设置小时时，保持

else                                            //分钟分情况+1
begin
if(fen1<6&&fen0<9) fen0<=fen0+1'b1;
else if(fen1<5&&fen0==9)
 begin
 fen0<=0;
 fen1<=fen1+1'b1;
 end
else
 begin
 fen1<=0;
 fen0<=0;
 end
end
end
endmodule

小时计数

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
module hour(
input CP,CR,setclock,dangwei,adjmode,JIN2,
output reg [3:0] hour1,hour0
    );
always @(posedge CP,negedge CR)
begin
if(~CR)               //清零
 begin
 hour1<=0;
 hour0<=0;
 end
 
else if(JIN2==0);      //无进位信号，保持

else if({setclock,dangwei,adjmode}==3'b010)//在设置模式且调整模式为减时，小时分情况-1
begin
if(hour0>0) hour0<=hour0-1'b1;
else if(hour1>0&&hour0==0)
 begin
 hour0<=4'b1001;
 hour1<=hour1-1'b1;
 end
else
 begin
 hour1<=4'b0010;
 hour0<=4'b0011;
 end
end

else if(setclock==0&&dangwei==0);    //设置分钟时，保持

else                                 //小时分情况+1
begin
if(hour1<2&&hour0<9) hour0<=hour0+1'b1;
else if(hour1<2&&hour0==9)
 begin
 hour0<=0;
 hour1<=hour1+1'b1;
 end
else if(hour1==2&&hour0<3) hour0<=hour0+1'b1;
else
 begin
 hour1<=0;
 hour0<=0;
 end
end
end
endmodule

译码显示

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
module xianshi(          //显示译码，将BCD码转为数码管的数字
input [3:0] Q,
output reg[6:0] show=0
  );
always@(Q)
begin
case(Q)
4'h0:show<=7'b100_0000;
4'h1:show<=7'b111_1001;
4'h2:show<=7'b010_0100;
4'h3:show<=7'b011_0000;
4'h4:show<=7'b001_1001;
4'h5:show<=7'b001_0010;
4'h6:show<=7'b000_0010;
4'h7:show<=7'b111_1000;
4'h8:show<=7'b000_0000;
4'h9:show<=7'b001_0000;
4'ha:show<=7'b000_1000;
4'hb:show<=7'b000_1100;
default:show<=7'b111_1111;
endcase
end
endmodule

通过扫掠显示数字

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
module showtime(
input CP0,EN,mode,showmode,
input [7:0]miao,fen,hour,alarmfen,alarmhour,
output reg[3:0]number=0,
output reg[7:0]guan=0
    );
integer k;
always@(posedge CP0)    //在1000Hz脉冲下，依次显示8个管子内容
begin

if(~EN) guan<=8'b1111_1111;   //熄屏

else if(mode==0)              //显示闹钟
begin
case(k)
0:begin 
number<=alarmfen[3:0];
guan<=8'b1110_1111;
k<=k+1;
end

1:begin
number<=alarmfen[7:4];
guan<=8'b1101_1111;
k<=k+1;
end

2:begin
if(showmode==1) number<=alarmhour[3:0];
else
begin                          //12小时制，显示调整
if((alarmhour[7:4]==1&&alarmhour[3:0]>2)||(alarmhour[7:4]==2&&alarmhour[3:0]>=2)) number<=alarmhour[3:0]-4'b0010;
else if(alarmhour[7:4]==2&&alarmhour[3:0]<2) number<=alarmhour[3:0]+4'b1000;
else if(alarmhour[7:4]==0&&alarmhour[3:0]==0) number<=4'b0010;
else number<=alarmhour[3:0];
end
guan<=8'b1011_1111;
k<=k+1;
end

3:begin
if(showmode==1) number<=alarmhour[7:4];
else
begin                         //12小时制，显示调整
if((alarmhour[7:4]==1&&alarmhour[3:0]>2)||(alarmhour[7:4]==2&&alarmhour[3:0]>=2)) number<=alarmhour[7:4]-4'b0001;
else if(alarmhour[7:4]==2&&alarmhour[3:0]<2) number<=0;
else if(alarmhour[7:4]==0&&alarmhour[3:0]==0) number<=4'b0001;
else number<=alarmhour[7:4];
end
guan<=8'b0111_1111;
k<=k+1;
end

4:begin
if(showmode==1) k<=0;
else
begin                        //12小时制，显示AM/PM
guan<=8'b1111_1110;
if(alarmhour[7:4]==2||(alarmhour[7:4]==1&&alarmhour[3:0]>=2)) number<=4'b1011;
else number<=4'b1010;
k<=0;
end
end

default:k<=0;
endcase
end

else                        //显示时钟，与闹钟相同，添加显示秒 
begin
case(k)
0:begin 
number<=miao[3:0];
guan<=8'b1111_1011;
k<=k+1;
end

1:begin
number<=miao[7:4];
guan<=8'b1111_0111;
k<=k+1;
end

2:begin
number<=fen[3:0];
guan<=8'b1110_1111;
k<=k+1;
end

3:begin
number<=fen[7:4];
guan<=8'b1101_1111;
k<=k+1;
end

4:begin
if(showmode==1) number<=hour[3:0];
else
begin
if((hour[7:4]==1&&hour[3:0]>2)||(hour[7:4]==2&&hour[3:0]>=2)) number<=hour[3:0]-4'b0010;
else if(hour[7:4]==2&&hour[3:0]<2) number<=hour[3:0]+4'b1000;
else if(hour[7:4]==0&&hour[3:0]==0) number<=4'b0010;
else number<=hour[3:0];
end
guan<=8'b1011_1111;
k<=k+1;
end

5:begin
if(showmode==1) number<=hour[7:4];
else
begin
if((hour[7:4]==1&&hour[3:0]>2)||(hour[7:4]==2&&hour[3:0]>=2)) number<=hour[7:4]-4'b0001;
else if(hour[7:4]==2&&hour[3:0]<2) number<=0;
else if(hour[7:4]==0&&hour[3:0]==0) number<=4'b0001;
else number<=hour[7:4];
end
guan<=8'b0111_1111;
k<=k+1;
end

6:begin
if(showmode==1) k<=0;
else
begin
guan<=8'b1111_1110;
if(hour[7:4]==2||(hour[7:4]==1&&hour[3:0]>=2)) number<=4'b1011;
else number<=4'b1010;
k<=0;
end
end

default:k<=0;
endcase
end
end

endmodule

设置闹钟

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
module setalarm(
input CP0,CR,seta,dangwei,adjmode,mode,
output reg [3:0] fen1,fen0,hour1,hour0
    );
always @(posedge CP0,negedge CR)
begin
if(~CR) 
begin
fen1<=0;
fen0<=0;
hour1<=0;
hour0<=0;
end

else if(mode==1||seta==1);       //不在闹钟调整模式时，保持

else if(dangwei==0&&adjmode==0)  //在设置分钟模式且调整模式为减时，分情况将分钟-1
begin
if(fen0>0) fen0<=fen0-1'b1;
else if(fen1>0&&fen0==0)
 begin
 fen0<=4'b1001;
 fen1<=fen1-1'b1;
 end
else
 begin
 fen1<=4'b0101;
 fen0<=4'b1001;
 end
end

else if(dangwei==0&&adjmode==1) //在设置分钟模式且调整模式为加时，分情况将分钟+1
begin
if(fen1<6&&fen0<9) fen0<=fen0+1'b1;
else if(fen1<5&&fen0==9)
 begin
 fen0<=0;
 fen1<=fen1+1'b1;
 end
else
 begin
 fen1<=0;
 fen0<=0;
 end
end

else if(dangwei==1&&adjmode==0) //在设置小时模式且调整模式为减时，分情况将小时-1
begin
if(hour0>0) hour0<=hour0-1'b1;
else if(hour1>0&&hour0==0)
 begin
 hour0<=4'b1001;
 hour1<=hour1-1'b1;
 end
else
 begin
 hour1<=4'b0010;
 hour0<=4'b0011;
 end
end

else                            //在设置小时模式且调整模式为加时，分情况将小时+1
begin
if(hour1<2&&hour0<9) hour0<=hour0+1'b1;
else if(hour1<2&&hour0==9)
 begin
 hour0<=0;
 hour1<=hour1+1'b1;
 end
else if(hour1==2&&hour0<3) hour0<=hour0+1'b1;
else
 begin
 hour1<=0;
 hour0<=0;
 end
end

end
endmodule

闹钟LED输出

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
module alarm(
input CP0,CR,startalarm,seta,setclock,
input [7:0] fen,hour,alarmfen,alarmhour,
output reg alarmCP
    );
reg[10:0] state;
always @(posedge CP0,negedge CR)                   //进行比对，若到达闹钟时间产生闹钟CP信号，用于控制闹钟的LED与声音输出
begin
if(~CR||~startalarm||~seta||~setclock||(fen!=alarmfen)||(hour!=alarmhour)) 
begin
alarmCP<=0;
state<=0;
end
else if(state==199||state==399||state==599||state==799||state==999||state==1199) //1.6s内产生在前四分之三部分的三个连续脉冲，即01010100脉冲，以此输出滴滴滴空滴滴滴空的声音
begin
state<=state+1'b1;
alarmCP<=~alarmCP;
end
else if(state==1599) state<=0;
else state<=state+1'b1;
end
endmodule

闹钟声音输出

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
module galarmsound(
input CP,alarmCP,startalarm,
output reg alarmsound
    );
integer k;
always @(posedge CP)
begin
if(startalarm==0)         //闹钟未开启
begin
k<=0; 
alarmsound<=0;
end

else if(alarmCP==0)       //alarmCP为0时，产生响度极小的声音
begin
if(k<1)
begin
alarmsound<=1'b1;
k<=k+1;
end
else if(k<9999)
begin 
alarmsound<=0;
k<=k+1;
end
else
begin
k<=0;
alarmsound<=1'b0;
end
end

else                  //alarmCP为1时，产生响度极大的声音
begin
if(k<999)
begin
alarmsound<=0;
k<=k+1;
end
else if(k<9999)
begin 
alarmsound<=1'b1;
k<=k+1;
end
else
begin
k<=0;
alarmsound<=0;
end
end

end

endmodule

整点亮灯

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
module zheng(
input CP2,CR,setclock,showmode,
input [7:0] fen,miao,hour,
output reg zhengLED
    );
integer k;
always@(posedge CP2,negedge CR)
begin
if(~CR||~setclock)
begin
k<=0;
zhengLED<=0;
end

else if(fen==0&&miao==0)               //整点报时，分24、12小时制报时，在24小时制下，0点闪烁24下
begin
case(hour)
8'b0010_0011:k<=showmode?46:22;
8'b0010_0010:k<=showmode?44:20;
8'b0010_0001:k<=showmode?42:18;
8'b0010_0000:k<=showmode?40:16;
8'b0001_1001:k<=showmode?38:14;
8'b0001_1000:k<=showmode?36:12;
8'b0001_0111:k<=showmode?34:10;
8'b0001_0110:k<=showmode?32:8;
8'b0001_0101:k<=showmode?30:6;
8'b0001_0100:k<=showmode?28:4;
8'b0001_0011:k<=showmode?26:2;
8'b0001_0010:k<=24;
8'b0001_0001:k<=22;
8'b0001_0000:k<=20;
8'b0000_1001:k<=18;
8'b0000_1000:k<=16;
8'b0000_0111:k<=14;
8'b0000_0110:k<=12;
8'b0000_0101:k<=10;
8'b0000_0100:k<=8;
8'b0000_0011:k<=6;
8'b0000_0010:k<=4;
8'b0000_0001:k<=2;
8'b0000_0000:k<=showmode?48:24;
default:k<=0;
endcase
end

else if(k>0)                           //k大于0时，LED翻转并将k-1，使得LED闪烁
begin
zhengLED<=~zhengLED;            
k<=k-1'b1;
end

else zhengLED<=0;

end

endmodule

整点亮灯的时钟产生

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
module zhengCP(
input CP,
output reg CLK=0
    );
reg [7:0] state;
always@(posedge CP)
begin
 if(state<165) state<=state+1'b1;//由1MHZ脉冲产生1KHZ脉冲，每计数166输出翻转一次
 else 
 begin
 CLK<=~CLK;
 state<=0;
 end
end
endmodule

RS触发器防抖动

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
module prevent(    //RS触发器，防止抖动
input CP,R,S,CPCLOCK,
output reg pCPCLOCK=0
    );
always@(posedge CP)
begin
case({R,S})
2'b00:pCPCLOCK<=CPCLOCK;
2'b01:pCPCLOCK<=1'b1;
2'b10:pCPCLOCK<=0;
2'b11:pCPCLOCK<=1'bx;
endcase
end

endmodule

管脚映射

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
NET "guan[0]" LOC = J17;
NET "guan[1]" LOC = J18;
NET "guan[2]" LOC = T9;
NET "guan[3]" LOC = J14;
NET "guan[4]" LOC = P14;
NET "guan[5]" LOC = T14;
NET "show[0]" LOC = T10;
NET "show[1]" LOC = R10;
NET "show[2]" LOC = K16;
NET "show[3]" LOC = K13;
NET "show[4]" LOC = P15;
NET "show[5]" LOC = T11;
NET "show[6]" LOC = L18;
NET "CP" LOC = E3;
NET "CR" LOC = J15;
NET "EN" LOC = L16;
NET "stop" LOC = M13;
NET "setclock" LOC = R15;
NET "dangwei" LOC = R17;
NET "adjmode" LOC = T18;
NET "seta" LOC = R13;
NET "mode" LOC = U8;
NET "startalarm" LOC = R16;
NET "alarmLED" LOC = H17;
NET "alarmonLED" LOC = U14;
NET "alarmsound" LOC = A11;
NET "alarmsoundEN" LOC=D12;
NET "showmode" LOC=T13;
NET "zhengLED" LOC=J13;
NET "set" LOC=N17;
NET "setmode" LOC=V10;

NET "guan[5]" IOSTANDARD = LVCMOS18;
NET "guan[4]" IOSTANDARD = LVCMOS18;
NET "guan[3]" IOSTANDARD = LVCMOS18;
NET "guan[2]" IOSTANDARD = LVCMOS18;
NET "guan[1]" IOSTANDARD = LVCMOS18;
NET "guan[0]" IOSTANDARD = LVCMOS18;
NET "show[6]" IOSTANDARD = LVCMOS18;
NET "show[5]" IOSTANDARD = LVCMOS18;
NET "show[4]" IOSTANDARD = LVCMOS18;
NET "show[3]" IOSTANDARD = LVCMOS18;
NET "show[2]" IOSTANDARD = LVCMOS18;
NET "show[1]" IOSTANDARD = LVCMOS18;
NET "show[0]" IOSTANDARD = LVCMOS18;
NET "CP" IOSTANDARD = LVCMOS18;
NET "CR" IOSTANDARD = LVCMOS18;
NET "EN" IOSTANDARD = LVCMOS18;
NET "stop" IOSTANDARD = LVCMOS18;
NET "setclock" IOSTANDARD = LVCMOS18;
NET "dangwei" IOSTANDARD = LVCMOS18;
NET "adjmode" IOSTANDARD = LVCMOS18;
NET "seta" IOSTANDARD = LVCMOS18;
NET "mode" IOSTANDARD = LVCMOS18;
NET "startalarm" IOSTANDARD = LVCMOS18;
NET "alarmLED" IOSTANDARD = LVCMOS18;
NET "alarmonLED" IOSTANDARD = LVCMOS18;
NET "alarmsound" IOSTANDARD = LVCMOS18;
NET "alarmsoundEN" IOSTANDARD = LVCMOS18;
NET "showmode" IOSTANDARD = LVCMOS18;
NET "zhengLED" IOSTANDARD = LVCMOS18;
NET "set" IOSTANDARD = LVCMOS18;
NET "setmode" IOSTANDARD = LVCMOS18;
# PlanAhead Generated physical constraints 

NET "guan[6]" LOC = K2;
NET "guan[7]" LOC = U13;

# PlanAhead Generated IO constraints 

NET "guan[7]" IOSTANDARD = LVCMOS18;
NET "guan[6]" IOSTANDARD = LVCMOS18;

NET "set" CLOCK_DEDICATED_ROUTE = FALSE;
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

//CR J15 复位到0
//EN L16 熄屏
//stop M13 停止计时
//setclock R15 调整时钟
//关闭R15并按下N17 小时+1
//关闭R15和R17 按下N17 分钟+1
//关闭R15和T18 按下N17 小时-1
//关闭R15和R17和T18 按下N17 分钟-1
//关闭R15和V10 每秒钟小时-1
//关闭R15和V10和T18 每秒钟分钟-1
//T13 调整12/24小时显示
//R13 闹钟开关
//U8 进入设置闹钟模式
//
技术
#FPGA
FPGA数字时钟的verilog代码实现
http://tsailooy.top/2024/03/26/verilog设计数字时钟/
作者
Tsailooy
发布于
2024年3月26日
更新于
2024年4月2日
许可协议